The Cleverscope system allows users to set two separate triggers with configurable edge direction (rising/falling), source channel, voltage threshold, and noise filters. Triggers can be logically combined using timing constraints (Trig1~2 < min, > max, or between min and max), or with event counting (e.g., “Trigger if Trigger 2 occurs 8 times after Trig1”).
The protocol decoding engine supports:
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SPI: Setup includes clock, data, and chip select inputs
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UART (TxD): Setup via analog or digital sources with selectable baud rate
Captured data can be decoded and exported using Notes, which are formatted with tab characters for direct Excel usage. The Get Frame button boosts sample transfer for full-resolution decoding, overcoming display buffer limitations.
Use cases demonstrated include validating SPI timing (e.g., CS* to CLK delay) and monitoring frequency-setting messages via UART. Engineers can use the dual-trigger logic to identify and isolate subtle timing violations across system conditions.
